Computer system that operates in VLIW and superscalar modes...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...

Reexamination Certificate

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Details

C712S023000, C712S024000

Reexamination Certificate

active

07111152

ABSTRACT:
Instructions in a computer system are executed in a plurality of parallel execution pipelines, a horizontal dependency check is carried out between instructions supplied to the parallel pipelines and in response to detecting horizontal dependency a control signal of a first or second type is generated depending on whether the dependency can be resolved by activating a by-pass or whether a temporary stall is required in one of the pipelines.

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patent: 5598546 (1997-01-01), Blomgren
patent: 5699537 (1997-12-01), Sharangpani et al.
patent: 5751984 (1998-05-01), Chang et al.
patent: 5826089 (1998-10-01), Ireton
patent: 5941983 (1999-08-01), Gupta et al.
patent: 5958042 (1999-09-01), Tremblay
patent: 5974537 (1999-10-01), Mehra
patent: 6480872 (2002-11-01), Choquette
patent: 0 399 762 (1990-11-01), None
patent: 0 551 090 (1993-07-01), None
Hennessy and Patterson, Computer Architecture—A Quantitative Approach, 2nd Edition, 1996, p. 189.
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2ndEdition,” 1996, pp. 146-154.
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2ndEdition,” 1996, pp. 278-281.
European Search Report from European Application No. 99410059.

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