Computer system that maintains system wide cache coherency durin

Details Computer system that maintains system wide cache coherency durin Computer system that maintains system wide cache coherency durin

1994-03-01

1997-10-28

Swann, Tod R.

395731, 395856, 395879, 395732, G06F 1318

Patent

active

056825161

ABSTRACT:
A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

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patent: 5265235 (1993-11-01), Sindha et al.
patent: 5426765 (1995-06-01), Stevens et al.
V. Popescu, et al., "The Metaflow Architecture", IEEE Micro, 1991, pp.10-13, and 63-73.
William W. Collier, "Reasoning About Parallel Architectures", entire book, Prentice Hall, 1992.

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