Patent
1997-03-28
1998-05-05
Lall, Parshotam S.
395477, G06F 938
Patent
active
057489378
ABSTRACT:
A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.
REFERENCES:
patent: 4773041 (1988-09-01), Hassler et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 4980824 (1990-12-01), Tulpule
patent: 5125083 (1992-06-01), Fite et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5280615 (1994-01-01), Church et al.
patent: 5420991 (1995-05-01), Konigsfeld et al.
patent: 5428761 (1995-06-01), Herlihy et al.
patent: 5542075 (1996-07-01), Ebcioglu et al.
V. Popescu, et al., "The Metaflow Architecture", IEEE Micro, 1991, pp. 10-13, and 63-73.
Mike Johnson, "Superscalar Microprocessor Design", Prentice Hall, pp. 31-163, 1991.
William W. Collier, "Reasoning About Parallel Architectures", Prentice Hall, 1992.
Abramson Jeffrey M.
Akkary Haitham
Glew Andrew F.
Hinton Glenn J.
Konigsfeld Kris G.
Intel Corporation
Lall Parshotam S.
Vu Viet
LandOfFree
Computer system that maintains processor ordering consistency by does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer system that maintains processor ordering consistency by, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system that maintains processor ordering consistency by will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-68389