Computer system permitting switching between architected and int

Details Computer system permitting switching between architected and int Computer system permitting switching between architected and int

1993-07-28

1994-01-18

Eng, David Y.

395775, 395800, G06F 930

Patent

active

052805930

ABSTRACT:
A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage "milli-instructions" and an interpretive execution "milli-mode". Additional hardware controlled instructions that are exclusively used in milli-mode may be added to provide additional controls or to improve performance (they augment the architected instruction set). Milli-mode routines intermingle milli-mode only instructions with architected instructions to implement complex functions. One milli-instruction called the DRAIN INSTRUCTION PIPELINE (DIP) causes the pipeline to drain selectively so the milli-programmer determines when and and what type of pipeline drain to perform. A DRAIN INSTRUCTION PIPELINE causes suspension of decoding until a selected event occurs. This DIP instruction includes options for suspending decoding until one of the following events have occurred: 1. all conceptually previous macro-instructions have completed; 2. all conceptually previous instructions have completed; 3. all store requests have reached the point where no exceptions would occur, but the actual store may not have completed; 4. all conceptually previous stores from all conceptually previous units-of-operation have competed (serialize); or 5. invalidate instruction buffers and fetch the next sequential macro-instructions.

REFERENCES:
patent: 4179736 (1979-12-01), Wilhite
patent: 4748559 (1988-05-01), Smith
patent: 4794517 (1988-12-01), Jones et al.

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