Computer system permitting mulitple write buffer read-arounds an

Details Computer system permitting mulitple write buffer read-arounds an Computer system permitting mulitple write buffer read-arounds an

1996-07-31

1997-12-09

Chan, Eddie P.

395445, 395250, G06F 1208

Patent

active

056969384

ABSTRACT:
A computer system is disclosed that permits multiple write buffer read-arounds. The system comprises a CPU (Central Processing Unit) for executing cycles for the computer system, a cache coupled to the CPU for storing data, a write buffer coupled to the CPU for receiving write data from the CPU, an arbiter to control bus accesses to the slave, and processing signals coupled between the cache and the write buffer for permitting the CPU to read-around the write buffer a plurality of times before the write data in the write buffer is flushed therefrom. The processing signals determine when the data stored in the write buffer is also stored in the cache, and, therefore, the cache is permitted to read-around the write buffer more than one time as long as the write buffer has the same data stored therein as exists in the cache.

REFERENCES:
patent: 4805098 (1989-02-01), Mills, Jr. et al.
patent: 5179679 (1993-01-01), Shoemaker
patent: 5418755 (1995-05-01), Nguyen et al.

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