Computer system including coprocessor devices simulating memory

Details Computer system including coprocessor devices simulating memory Computer system including coprocessor devices simulating memory

1995-02-07

1998-08-04

Harrity, John E.

395500, 395503, 395527, G06F 944

Patent

active

057908818

ABSTRACT:
A method and system for coupling a coprocessor to a master device, in which the coprocessor emulates an memory interface to the master device, like that of a memory device. The coprocessor is coupled to a memory bus and receives memory accesses directed to a set of addresses not covered by memory devices also coupled to the memory bus. The coprocessor is disposed to receive data written from the master device, perform a coprocessing function on that data, and respond to a read data command from the master device with processing results. The coprocessor uses memory block transfers to read data from and write data to memory devices also coupled to the memory bus. A general purpose computer system comprises a central processor and memory coupled to a PCI bus, a graphics processor and graphics memory coupled to the PCI bus, and a coprocessor coupled to the graphics processor and graphics memory. The coprocessor is adapted to compute, in response to data written to it by the graphics processor, a graphical function such as a 3D processing function, MPEG video compression or decompression, a raytracing function, or some related function in support of graphics processing. The coprocessor may communicate with the central processor and its memory using a memory access operation performed by the central processor, and may communicate with the graphics memory using a memory block transfer performed by the graphics processor. The coprocessor may emulate a memory wait condition or memory wait state using read-ready and write-ready flags which are readable by software executing on the general processor.

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