Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Patent
1998-05-13
2000-02-29
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
712 23, 712214, 712215, 712217, 712218, G06F 930
Patent
active
060322519
ABSTRACT:
A computer system including a microprocessor employing a reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration. Concurrently decoded instructions are stored into a line of storage, and the concurrently decoded instructions are retired as a unit. A last in line (LIL) indication is stored for each instruction in the line. The LIL indication indicates whether or not the instruction is last within the line storing that instruction to update the storage location defined as the destination of that instruction. The LIL indications for a line can be used as write enables for the register file.
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Tran Thang M.
Witt David B.
Advanced Micro Devices , Inc.
An Meng-Ai T.
El-Hady Nabil
Merkel Lawrence J.
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