Computer system in which a bus controller varies data transfer r

Details Computer system in which a bus controller varies data transfer r Computer system in which a bus controller varies data transfer r

1992-03-31

1994-01-18

Fleming, Michael R.

Boots, shoes, and leggings

395325, 395550, 364DIG1, 3642315, 3642362, 364238, 3642391, 364240, 3642405, 3642423, 3642426, 3642427, 3642472, 3642549, 364260, 3642601, 364270, 3642702, 3642716, G06F 1300

Patent

active

052805875

ABSTRACT:
A computer system includes a bus and a plurality of devices coupled to the bus. A CPU within the bus controller generates addresses for data transfers to and from the devices. A bus controller generates control signals for the data transfers. A data transfer rate controlled by the control signals is varied so that the data transfer rate is optimal for data transfers to and from each device. The data transfer rate for a data transfer to or from a first device is based on a subset of address bits used by the CPU to address the first device.

REFERENCES:
patent: 4095265 (1978-06-01), Urba
patent: 4217637 (1980-08-01), Faulkner et al.
patent: 4476527 (1984-10-01), Clayton, IV
patent: 4486833 (1984-12-01), Daudelin
patent: 4494196 (1985-01-01), Greer
patent: 4507732 (1985-03-01), Catiller et al.
patent: 4571674 (1986-02-01), Hartung
patent: 4607348 (1986-08-01), Sheth
patent: 4644463 (1987-02-01), Hotchkin et al.
patent: 4860193 (1989-08-01), Bentley et al.

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