Patent
1996-09-18
1999-03-02
Treat, William M.
395822, G06F 1342
Patent
active
058782729
ABSTRACT:
A computer system has a central processing unit ("CPU") and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal ("IRDY"), a device select signal ("DEVSEL"), and a target ready signal ("TRDY"). First and second direct memory access devices ("DMA") are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.
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Nakano Masayoshi
Taniguchi Masayoshi
Yanagisawa Takashi
Caldwell Andrew
International Business Machines Corp.
McConnell Daniel E.
Treat William M.
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