Patent
1993-05-26
1995-01-10
Lall, Parshotam S.
395325, 395700, G06F 1314
Patent
active
053815416
ABSTRACT:
A multiprocessor computer includes a planar board and a processor card mounted on the planar board. An interrupt controller is mounted on the planar board and has a plurality of interrupt input lines for receiving interrupt requests from a plurality of interrupting devices. The interrupt controller also has an output line that transmits an interrupt to the processor card. The processor card includes an interrupt director having a plurality of interrupt request lines respectively connected to interrupt request pins of the different processors. The director is also connected to the output line coming from the interrupt controller. In response to receiving an interrupt request from the interrupt controller, the director performs an interrupt acknowledge cycle and transmits an interrupt request, on only one of the interrupt request lines, to a specific processor predetermined by the director. The specific processor then reads an interrupt vector from the director. The interrupt vector uniquely identifies the interrupt level and is used by the processor to execute an interrupt handler for that specific interrupt level.
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Begun Ralph M.
Turner Michael R.
Babayi Robert S.
International Business Machines Corp.
Lall Parshotam S.
Vu Viet
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