Electrical computers and digital processing systems: multicomput – Distributed data processing – Client/server
Reexamination Certificate
2001-08-14
2003-07-01
Jean, Frantz B. (Department: 2155)
Electrical computers and digital processing systems: multicomput
Distributed data processing
Client/server
C710S002000, C710S114000, C710S311000
Reexamination Certificate
active
06587868
ABSTRACT:
TECHNICAL FIELD
The present invention relates to computer systems, and more particularly, to a method of configuring a computer system with a peer to peer arrangement of computer buses.
BACKGROUND OF THE INVENTION
A computer system typically includes a central processing unit (CPU) coupled by communication pathways known as computer buses to various computer components, such as memory, input devices, and a video monitor. To enable the CPU to communicate with the computer components, the computer components must be configured to communicate in an organized manner. Typically, each computer device includes a set of configuration registers that store configuration data, such as data identifying the type and capabilities of the computer device. Some of the configuration data, such as the device type, is provided with the computer device by the device manufacturer. In addition, the CPU typically provides each computer device with additional configuration data that defines how the computer devices will interact with each other and with the CPU.
Virtually all computer devices utilize some memory address space, input/output (I/O) address space or both. When the computer system is turned on, the computer system must be configured so that each computer device's I/O and memory functions occupy mutually exclusive address ranges. After determining how much memory and I/O space a computer device requires, the CPU assigns the computer device I/O and/or memory address ranges that do not conflict with I/O and memory address ranges assigned to any other computer device of the computer system.
A block diagram of a typical prior art computer system
10
, employing a hierarchical architecture of computer buses, is shown in FIG.
1
. The computer system
10
includes a computer processor
12
coupled by a host bus
14
to a read-only memory (ROM) device
16
, a host-PCI bridge
18
and a memory controller
20
coupled to a system memory module
22
. Coupled to the host-PCI bridge
18
by a first Peripheral Component Interconnect (PCI) bus
24
are a PCI-ISA bridge
26
, first PCI-PCI bridge
28
, and second PCI-PCI bridge
30
. The PCI-ISA bridge
26
couples the first PCI bus
24
to an industry standard architecture (ISA) bus
32
which is coupled to an input device
34
and a floppy drive
36
. The first PCI-PCI bridge
28
couples the first PCI bus
24
to a second PCI bus
38
, which is coupled to a video controller
40
and a hard drive
42
. The second PCI-PCI bridge
30
couples the first PCI bus
24
to a third PCI bus
44
, which is coupled to a network adapter
46
and a fax-modem
48
.
When the computer system
10
is turned on, the processor
12
configures the computer system
10
based on computer instructions of basic input/output system (BIOS) routines
50
stored in the ROM device
16
. The BIOS routines
50
are hardware-specific in that the manufacturer of the computer system
10
designs the BIOS routines specifically for the particular implementation of the computer system
10
being sold. As a result, any configuration of computer buses and computer devices can be employed without limiting the ability of the computer system to be configured by the BIOS routines
50
. The BIOS is the only agent responsible for configuring the PCI-PCI bridges, because interrupts for each bus must be routed by the BIOS.
One drawback of configuring the computer system
10
using the hardware-specific BIOS routines
50
is that only computer devices designed according to the configuration rules implemented by the BIOS routines
50
can be added to the computer system
10
. The PCI specification is being modified to allow the interrupt routing to be performed by the computer's operating system, such as Microsoft Windows™ and Microsoft Windows NT™. As a result, the operating system must be allowed to configure PCI-PCI bridges using the configuration format defined by the “PCI-PCI Bridge Architecture Specification” issued by the PCI Special Interest Group on Apr. 5, 1994, which is incorporated herein by reference. Such changes to the PCI specification may reduce compatibility problems, but do not provide the operating system with a method of configuring computer systems that do not employ the traditional hierarchical architecture of the computer system
10
shown in FIG.
1
.
SUMMARY OF THE INVENTION
An embodiment of the present invention is directed to a method of configuring a computer system having a processor coupled by a host bus to first and second bus devices. The processor transmits on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.
Another aspect of the invention is directed to a method of configuring first and second PCI bridges in a computer system having a processor coupled by a host bus to the PCI bridges. The first PCI bridge couples a first PCI bus to the host bus and the second PCI bridge couples a second PCI bus to the host bus. The processor transmits on the host bus a configuration command that includes a device identifier that identifies the second PCI bridge and a bus identifier that identifies the first PCI bus. Upon receiving the configuration command from the host bus, the second PCI bridge responds to the configuration command such that the second PCI bridge appears to be directly coupled to the first PCI bus when the second PCI bridge is actually indirectly coupled to the first PCI bus via the host bus and the first PCI bridge.
REFERENCES:
patent: 4589063 (1986-05-01), Shah et al.
patent: 5379431 (1995-01-01), Lemon et al.
patent: 5568619 (1996-10-01), Blackledge et al.
patent: 5640570 (1997-06-01), St. Clair et al.
patent: 5734847 (1998-03-01), Garbus et al.
patent: 5734850 (1998-03-01), Kenny et al.
patent: 5751975 (1998-05-01), Gillespie et al.
patent: 5754436 (1998-05-01), Walsh et al.
patent: 5761458 (1998-06-01), Young et al.
patent: 5790831 (1998-08-01), Lin et al.
patent: 5819112 (1998-10-01), Kusters
patent: 5832245 (1998-11-01), Gulick
patent: 5838899 (1998-11-01), Leavitt et al.
patent: 5838935 (1998-11-01), Davis et al.
patent: 5848249 (1998-12-01), Garbus et al.
patent: 5854910 (1998-12-01), Gulick
patent: 5867730 (1999-02-01), Leyda
patent: 5878237 (1999-03-01), Olarig
patent: RE36191 (1999-04-01), Solomon
patent: 5960213 (1999-09-01), Wilson
patent: 5978865 (1999-11-01), Hansen et al.
patent: 5983303 (1999-11-01), Sheafor et al.
patent: 6052513 (2000-04-01), MacLaren
patent: 6092141 (2000-07-01), Lange
patent: 6119192 (2000-09-01), Kao et al.
patent: 6317803 (2001-11-01), Rasmussen et al.
PCI Local Bus, “PCI to PCI Bridge Architecture Specification,” Revision 1.0, Apr. 5, 1994, pp. 1-66.
Dorsey & Whitney LLP
Jean Frantz B.
LandOfFree
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