Computer system having an internal cach microprocessor slowdown

Details Computer system having an internal cach microprocessor slowdown Computer system having an internal cach microprocessor slowdown

1989-11-03

1993-08-31

Lee, Thomas C.

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3642295, 3642455, 36424691, 3642473, 3642517, 3642549, 3642551, 3642558, 36424231, 3642423, 36424234, 36424291, 36424341, 36424345, 3642434, 3642433, 364DIG1, 364DIG2, G06F 9302, G06F 1208, G06F 1204, G06F 1202

Patent

active

052416810

ABSTRACT:
A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with applications software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

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Proceedings "1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors", Oct. 2-4, 1989, pp. 192-198.

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