Patent
1997-01-07
1998-07-21
Ellis, Richard L.
395389, G06F 9318
Patent
active
057845859
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to computer systems, and more specifically to systems in which the memory bus width is less than the word width used by the processor.
The present invention finds particular application in RISC systems (RISC standing for Reduced Instruction Set Computer), although it is not restricted to such systems. RISC systems are so called in contrast to systems based on conventional microprocessors such as the well-known 80286, 80386, and 80486 microprocessors, which are called CISC (Complex Instruction Set Computer) processors.
RISC is a design or system which uses instructions which are generally simpler than the instructions used by CISC systems. The intention of the RISC design is that the gain in the execution time of individual instructions should outweigh the loss of speed due the increased number of instructions. One of the features used in RISC designs to achieve increased speed is that the amount of processing of instructions should be reduced, and one technique used to achieve this is to use long instructions, so that many of the bits and fields in the instructions can be used directly instead of having to be decoded. For similar reasons of speed and for general convenience, RISC systems also tend to. use a relatively long data word length, matching the instruction word length. Thus one well-established RISC system is the ARM (Advanced RISC Machine) core (ie processor), which is a 32-bit system.
Memories and memory access buses are however normally relatively narrow (short in terms of word length), typically 8 or 16 bits. Wide memory systems and buses are of course possible, but for a variety of reasons (including the fact that wide memories are relatively expensive), are relatively uncommon. It is therefore not unusual for a computer system to comprise an 8 or 16 bit wide memory coupled to a 32-bit processor.
This obviously involves a mismatch between the memory width and the processor word width. This mismatch is normally overcome by the use of buffer latches. A set of four 8-bit latches is coupled to an 8-bit or 16-bit memory bus and to a 32-bit processor bus; data is loaded into the latches and read from them on the memory side in 4 cycles of 8-bit words or 2 cycles of 16-bit words, and is loaded into and read from them on the processor side in single 32-bit word cycles.
The general object of the present invention is to provide, in a system in which the memory bus width is less than the word width used by the processor, an improvement in the matching of the memory and processor buses.
According to the present invention there is provided a computer system comprising a memory, a processor, means for passing instructions from the memory to the processor, and compressed instruction pre-processing means for expanding compressed instructions, characterized in that the compressed instruction pre-processing means comprise: combination in an instruction coming from the memory; full length; and detector circuit, passes either the original instruction or the output of the compressed instruction decoder to the processor.
A system is known, from JP 5 324 314 A, Hitachi (Patent Abstracts of Japan, vol 018, no 153 (P-1079), 14.03.94), in which the memory space occupied by a program is reduced by compressing the instructions (using a public compression algorithm). In that system, the entire program (ie all instructions) is decompressed between the memory and the instruction register.
The main systems to which the present invention is applicable have two characteristics, relating to the instruction format and the way instructions are extracted from memory. The instruction format for the processor includes a condition field the contents of which indicate the conditions under which the instruction is executed; one of the codes which the condition field can include is an NV code indicative that the instruction is not to be executed (NV=Never). An instruction is extracted from memory, ie passed from the memory bus to the processor, via a set of buffers which are loaded sequentially with words
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Ellis Richard L.
Hackbart Rolland R.
Motorola Inc.
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