Computer system configuration via test bus

Details Computer system configuration via test bus Computer system configuration via test bus

1991-11-27

1994-08-30

Atkinson, Charles E.

Excavating

395575, G01R 3128

Patent

active

053434781

ABSTRACT:
System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough. The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. If memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus. To ensure proper operation with such devices, a pacing or ready signal is generated such that access is delayed until the requested access can be successfully completed.

REFERENCES:
patent: 4225957 (1980-09-01), Doty, Jr. et al.
patent: 4597080 (1986-06-01), Thatte et al.
patent: 4621363 (1986-11-01), Blum
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4701921 (1987-10-01), Powell et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4853929 (1989-08-01), Azuma et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 4918379 (1990-04-01), Jongepier
patent: 5115191 (1992-05-01), Yoshimori
patent: 5173904 (1992-12-01), Daniels et al.
patent: 5222068 (1993-06-01), Burchard
IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE STD 1149.1-1990, May 21, 1990.
The Wall Street Journal, Sep. 19, 1990 Edition, Advertisement, pp. A16-A17.

Affiliated with

Also associated with

Rating

Computer system configuration via test bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer system configuration via test bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system configuration via test bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-35120