Patent
1996-03-01
1998-03-31
Sheikh, Ayaz R.
G06F 126
Patent
active
057349142
ABSTRACT:
There is provided a computer system including a system memory operable with a first voltage level, a processor operable with a second voltage level different from the first voltage level, and capable of accessing the system memory to perform burst read, a data bus connected to the processor, and a level shifter connected between the system memory and the data bus for shifting the voltage level of a data signal supplied from the system memory and transferring the level-shifted data signal to the data bus, the level shifter including a latch circuit for sequentially latching, at predetermined interval, a plurality of n-bit data which constitute the level-shifted data signal, to thereby minimize the interval between each adjacent pair of the n-bit data.
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Nakamura Nobutaka
Senuma Koichi
Kabushiki Kaisha Toshiba
Sheikh Ayaz R.
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