Computer system cache performance on write allocation cycles by

Details Computer system cache performance on write allocation cycles by Computer system cache performance on write allocation cycles by

1994-10-14

1997-12-16

Chan, Eddie P.

395470, G06F 1208

Patent

active

056995504

ABSTRACT:
In a microcomputer system implementing a cache memory subsystem, the cache performance on write allocation cycles is improved. When the processor writes to a line of the cache memory that results in a cache tag miss, after the processor write operation is suspended, the data is allocated from main memory into the cache memory. During this main memory read, however, instead of setting the state of the line of memory to unmodified, its state is set to modified. On the subsequent processor read operation, a cycle is saved because the modified bit does not have to be changed from unmodified to modified.

REFERENCES:
patent: 5060136 (1991-10-01), Furney et al.
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5488709 (1996-01-01), Chan
Handy, "The Cache Memory Book", 1993, p. 62-64, 69-72, 262.
Pentium.TM. Processor User's Manual, vol. 2:82496 Cache Controller and 82491 Cache SRAM Data Book, .COPYRGT.Intel Corporation 1993, pp. 2-1 to 2-4;3-1; 3-5 to 3-7; 3-10 to 3-11; 5-1 to 5-10; 5-90 to 5-91; 6-14 to 6-15 .

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