Computer system architecture employing cache data line move-out

Details Computer system architecture employing cache data line move-out Computer system architecture employing cache data line move-out

1986-09-19

1989-11-14

Clark, David L.

Boots, shoes, and leggings

G06F 1300

Patent

active

048811637

ABSTRACT:
A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.

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patent: 4040027 (1977-08-01), Van Es et al.
patent: 4217640 (1980-08-01), Porter et al.
patent: 4298929 (1981-11-01), Capozzi
patent: 4467414 (1984-08-01), Akagi et al.
Fletcher R. P. and Marti D. B., "Stove Buffer," IBM Technical Disclosure Bulletin, vol. 25, No. 9, pp. 4522-4526.

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