Computer system apparatus for prefetching data requested by a pe

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G06F 700

Patent

active

043719244

ABSTRACT:
A computer system apparatus is disclosed for improved handling of requests by a peripheral device for data from memory. The apparatus serially receives multiple memory addresses from which data is requested by the peripheral device, and makes a determination that the received addresses form a sequence in memory. Upon this determination, the apparatus begins prefetching data from addresses anticipated to be received from the peripheral device, as an extension of the address sequence received. This prefetching of data, without waiting for an anticipated address to actually be received from the peripheral device, permits the apparatus of the invention to be simultaneously performing reads to memory and communication with the requesting peripheral device. This decreases the access time on the peripheral bus, providing increased bus rates and thereby improving computing throughput.

REFERENCES:
patent: 3825904 (1974-07-01), Burk et al.
patent: 3928857 (1975-12-01), Carter et al.
patent: 4086629 (1978-04-01), Desyllas et al.
patent: 4095269 (1978-06-01), Kawabe et al.
patent: 4179737 (1979-12-01), Kim

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