Computer system and method with integrated level and edge interr

Details Computer system and method with integrated level and edge interr Computer system and method with integrated level and edge interr

1995-02-17

1996-09-10

Harvey, Jack B.

395868, G06F 946

Patent

active

055554130

ABSTRACT:
A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

REFERENCES:
patent: 4023143 (1977-05-01), Braunstein
patent: 4764864 (1988-08-01), Takane
patent: 5261107 (1993-11-01), Klim et al.
patent: 5381541 (1995-01-01), Begun et al.
patent: 5410710 (1995-04-01), Sarangdhar et al.
patent: 5438677 (1995-08-01), Adams et al.

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