Computer system and method for maintaining memory consistency in

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395444, 395446, 395449, 395471, 395473, 395483, 395859, 395861, 364DIG1, G06F 1200

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056236280

ABSTRACT:
A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

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"The Metaflow Architecture", pp. 10-13 and 63-73, by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, and David Isaman, IEEE Micro, 1991.
GB 1555300 A (IBM), by Eugene Joseph Annunziata, Robert Sidney James and Kwang Gun Tan.
GM 1313530 A (IBM) by Philip Simon Dauber Russell John Robelen and John Randolph Wierzbicki.
"Supersalar Microprocessor Design" by Mike Johnson, Advanced Micro Devices, Prentice Hall, 1991. P6S 1-287.

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