Computer subsystem reset by address dependent RC discharge

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Details

3642599, 3642802, 3642803, 364DIG1, 395575, 371 12, G06F 124

Patent

active

053982657

ABSTRACT:
In a system wherein a system master (11) communicates with a plurality of subsystems (13, 25, 27, 29), each subsystem (13, 25, 27, 29) is associated with a unique reset address and a reset circuit which recognizes that reset address and generates a reset signal. Each reset circuit includes an address decoder (15) for decoding the reset address to produce a signal which closes a logic gate switch (19). The logic gate switch (19) is repeatedly closed in response to repeated assertions of the address to successively discharge the voltage on a capacitor (C). When the capacitor voltage is discharged to a selected level, a buffer level detector circuit (23) generates the reset signal.

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