Computer program product for enabling a computer to remove redun

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364488, G06F 1750

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active

057743690

ABSTRACT:
A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.

REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4591993 (1986-05-01), Griffin et al.
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4726023 (1988-02-01), Carter et al.
patent: 4816999 (1989-03-01), Berman et al.
patent: 4862399 (1989-08-01), Freeman
patent: 4916627 (1990-04-01), Hathaway
patent: 5029102 (1991-07-01), Drumm et al.
patent: 5140526 (1992-08-01), McDermith et al.
"A Rule-Based System for Optimizing Combinational Logic", de Geus et al., IEEE Design and Test, pp. 22-32, 1985.
J.C. Sutton, III and J.G. Bredeson, "Minimal Redundant Logis for High Reliability and Irredundant Testability", IEEE Transactions On Computers, vol. c-29, No. 7, pp. 648-656, Jul., 1980.
J.A. Darringer, W.H. Joyner, Jr., C.L. Berman and L. Trevillyan, "Logic Synthesis Through Local Transformations", IBM J. Res. Develop., vol. 25, No. 4, pp. 272-280, Jul., 1981.
R.K. Brayton, "Factoring logic functions", IBM J. Res. Development, vol. 31, No. 2, pp. 187-190, Mar., 1987.
K.A. Bartlett, et al., "Multilevel Logic Minimization Using Implicit Don't Cares", IEEE Transactions on Computers, vol. c-32, No. 10, pp. 947-952, Oct., 1983.
L. Trevillyan, W. Joyner and L. Berman, "Global Flow Analysis in Automatic Logic Design", IEEE Transactions on Computers, vol. c-35, No. 1, pp. 77-81, Jan., 1986.
R. Dandapani and S.M. Reddy, "On the Design of Logic Networks with Redundancy and Testability Considerations", IEEE Transactions on Computers, vol. c-23, No. 11, pp. 1139-1149, Nov., 1974.
J.P. Roth, "Minimization by the D Algorithm", IEEE Transactions On Computers, vol. c-35, No. 5, pp. 476-478, May, 1986.
T.F. Schwab and S.S. Yau, "An Algebraic Model of Fault-Masking Logic Circuits", IEEE Transactions on Computers, vol. c-32, No. 9, pp. 809-825, Sep., 1983.
D. Brand, "Redundancy and Don't Cares in Logic Synthesis", IEEE Transactions on Computers, vol. c-32, No. 10, pp. 947-952, Oct., 1983.
R.K. Brayton et al., "MIS: A Multiple-Level Logic Optimization System", IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 6, pp. 1062-1080, Nov., 1987.
C.C. Chao, "AC Test Pattern Generation For Sequential Logic", IBM Technical Disclosure Bulletin, vol. 16, No. 8, pp. 2439-2441, Jan., 1974.
D. Brand, "Detecting Redundancy And Don't Cares In Logic Circuit Design", IBM Technical Disclosure Bulletin, vol. 26, No. 7A, pp. 3456-3463, Dec., 1983.
R.K. Brayton, C.L. Chen and J. Yamour, "Method For Optimizing Logic For Single-Ended Domino Logic Circuits", IBM Technical Disclosure Bulletin, vol. 27, No. 78, pp. 4398-4401, Dec., 1984.
D.E. Popp, "Method For Removing Redundancies From Programmable Logic Arrays", IBM Technical Disclosure Bulletin, vol. 28, No. 10, pp. 4677-4682, Mar., 1986.
W.B. Perlowitz, "Detection of Multiplexer Structures In Logic", IBM Technical Disclosure Bulletin, vol. 30, No. 7, pp. 36-38, Dec., 1987.
J.L. Gilkinson and R.C. Itskin, "Iterative Consensus And Absorption", vol. 30, No. 9, pp. 379-380, Feb., 1988.
D.O. Forlenza, et al., "Test Generation of AC Faults Using Weighted Random Patterns", IBM Technical Disclosure Bulletin, vol. 32, No. 3A, pp. 4-6, Aug., 1989.

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