Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-08-09
2011-08-09
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S136000
Reexamination Certificate
active
07996800
ABSTRACT:
System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm. The exhaustive search includes performing an exhaustive satisfiability search by propagating a binary decision diagram (BDD) through the netlist.
REFERENCES:
patent: 6253365 (2001-06-01), Baldwin
patent: 7017096 (2006-03-01), Abramovici
patent: 7047139 (2006-05-01), Shtrichman
patent: 7478344 (2009-01-01), Baumgartner et al.
Baumgarter Jason Raymond
Kanzelman Robert Lowell
Mony Hari
Paruthi Viresh
Anthony VS England
Dillon Justin
International Business Machines - Corporation
Siek Vuthe
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