Coded data generation or conversion – Digital code to digital code converters – To or from nrz codes
Reexamination Certificate
2003-03-28
2004-02-10
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from nrz codes
C341S067000, C341S069000
Reexamination Certificate
active
06690308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a modulation method, a modulation apparatus, a demodulation method, a demodulation apparatus, an information recording medium, an information transmission method, and an information transmission apparatus.
2. Description of the Related Art
Some modulation (encoding) procedures used for digital signals recorded on recording mediums are of a (1, 7) RLL type, where “(1, 7) RLL” means run length limiting rules such that 1 to 7 successive bits of “0” should be between bits of “1” in a modulation-resultant bit stream. The (1, 7) RLL modulation tends to insufficiently suppress DC and near-DC components of a modulation-resultant bit stream. Therefore, in specified conditions, the spectrum of an information signal enters a frequency band assigned to a servo signal. In this case, the information signal interferes with servo control.
Japanese patent application publication number 6-195887/1994 discloses first and second modulation apparatuses. The first modulation apparatus in Japanese application 6-195887 processes an input signal which has a sequence of symbols each having one byte. The first modulation apparatus includes an inverting circuit, a parallel-to-serial converting circuit, and a (1, 7) RLL modulation circuit. The inverting circuit receives the input signal, and inverts all bits in every odd-numbered symbol. The inverting circuit keeps every even-numbered symbol unchanged. The output signal from the inverting circuit is converted into a first bit stream by the parallel-to-serial converting circuit. The (1, 7) RLL modulation circuit subjects the first bit stream to (1, 7) RLL modulation, thereby generating a modulation-resultant bit stream (a second bit stream). The inversion of every odd-numbered symbol by the inverting circuit causes the suppression of a DC component of the modulation-resultant bit stream.
The second modulation apparatus in Japanese application 6-195887 includes a randomizing circuit and a (1, 7) RLL modulation circuit. The randomizing circuit receives an input signal, and randomizes the input signal. The randomizing circuit outputs the randomizing-resultant signal to the (1, 7) RLL modulation circuit. The (1, 7) RLL modulation circuit subjects the randomizing-resultant signal to (1, 7) RLL modulation, thereby generating a modulation-resultant bit stream. The signal processing by the randomizing circuit causes the suppression of a DC component of the modulation-resultant bit stream.
Japanese patent application publication number 10-340543/1998 discloses (1, 7) RLL modulation provided with DSV (digital sum variation) control for suppressing DC and low-frequency components of a modulation-resultant bit stream. According to the (1, 7) RLL modulation in Japanese application 10-340543, three successive bits in every prescribed position in a (1, 7) RLL code string is replaced by six successive DSV control bits of a pattern chosen so that the rules “(1, 7) RLL” will be observed.
Japanese patent application publication number 2000-332613 discloses a 4-6 modulator. The 4-6 modulator contains a set of four different encoding tables. The 4-6 modulator converts or encodes every 4-bit input code word into a 6-bit output code word by, referring to the set of the encoding tables. The 6-bit output code word forms a 6-bit block of a modulation-resultant bit stream. Each of the encoding tables stores 6-bit output code words assigned to 4-bit input code words respectively. In addition, the encoding tables contain next-table selection numbers accompanying the respective 6-bit output code words therein. Each of the next-table selection numbers designates one among the encoding tables which will be used to convert a next 4-bit input code word. The output code words and the next-table selection numbers in the encoding tables are designed so that the modulation-resultant bit stream formed by a succession of selected output code words will follow (1, 7) RLL. First and second specified ones of the encoding tables are designed so that 6-bit output code words in the first specified encoding table which correspond to prescribed 4-bit input code words will be opposite in polarity (“odd-even” in the number of “1”) to those of 6-bit output code words in the second specified encoding table.
In the 4-6 modulator of Japanese application 2000-332613, two candidate 6-bit output code words may be selected from the first and second specified encoding tables in response to a given 4-bit input code word. DSVs (digital sum variations) are calculated for the candidate 6-bit output code words, respectively. The absolute values of the DSVs are compared. One of the candidate 6-bit output code words which corresponds to the smaller of the absolute values of the DSVs is selected as a final 6-bit output code word. In this way, DSV control is implemented.
Japanese application 2000-332613 further discloses a demodulation apparatus including a 6-4 demodulator. In Japanese application 2000-332613, the 6-4 demodulator recovers encoding-table designation information from a sequence of 6-bit code words. The encoding-table designation information represents which of encoding tables has been used in generating a code word immediately following a code word of interest. The 6-4 demodulator decodes the code word of interest into an original code word by referring to a decoding table in response to the recovered encoding-table designation information.
Japanese patent application publication number 11-346154/1999 discloses a modulation apparatus, a modulation method, a demodulation apparatus, a demodulation method, a providing medium related to the modulation apparatus, and a providing medium related to the demodulation apparatus. The modulation apparatus in Japanese application 11-346154 includes an inserting section which adds DSV control bits to an input data sequence. The inserting section outputs the DSV-control-bit-added data to a modulator. The modulator handles the output data from the inserting section as data having a basic data length of 2 bits. According to a conversion table, the modulator converts the output data from the inserting section into data of a variable length code having a basic data length of 3 bits. The modulator outputs the variable-length-code data to an NRZI converter. The conversion table has a replacement code for restricting succession of a minimum run to a prescribed number of times or less, and a replacement code for observing run length limiting rules. The conversion table further has a conversion rule such that the remainder in the division of the number of bits of “1” in an element of a data sequence by 2 and the remainder in the division of the number of bits of “1” in an element of a code word sequence by 2 are equal to each other as 1 or 0. Thus, the data sequence and the code word sequence are equal in polarity (“odd-even” in the number of bits of “1” in an element).
SUMMARY OF THE INVENTION
It is a first object of this invention to provide a modulation method which is excellent in encoding rate (encoding efficiency) and DC-component suppression.
It is a second object of this invention to provide a modulation apparatus which is excellent in encoding rate and DC-component suppression.
It is a third object of this invention to provide a demodulation method which is excellent in encoding rate and DC-component suppression.
It is a fourth object of this invention to provide a demodulation apparatus which is excellent in encoding rate and DC-component suppression.
It is a fifth object of this invention to provide an information recording medium which is excellent in encoding rate and DC-component suppression.
It is a sixth object of this invention to provide an information transmission method which is excellent in encoding rate and DC-component suppression.
It is a seventh object of this invention to provide an information transmission apparatus which is excellent in encoding rate and DC-component suppression.
A first aspect of this invention provides a modulation method comprising the steps of generating
Mai Lam
Tokar Michael
Victor Company of Japan Ltd.
Woo Louis
LandOfFree
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