Computer program debugging system

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371 12, 371 5, G06F 1100

Patent

active

047559977

ABSTRACT:
A program debugging system for a computer having an arithmetic/logic controller for implementing operations for data in accordance with a stored program and a program debugging device for issuing commands for correcting program errors to the arithmetic/logic controller, the system comprising a readout data addressing unit incorporated in the program debugging device for specifying the address of data which has caused an error in the arthmetic/logic controller, an address setting memory for writing the address specified by the readout data addressing unit into the arithmetic/logic controller, a data readout commander incorporated in the program debugging device for commanding the readout of the error-causing data in response to the input command issued on an input console provided in the program debugging device, a data hold/transfer unit for reading out data in the address set in compliance with the detection by an error detector in the arithmetic/logic controller and delivering it to a data receive/edit unit in the program debugging device, the data receive/edit unit receiving data from the data hold/transfer unit, editing the received data, and displaying the edited data on a display unit via a display controller.

REFERENCES:
patent: 4308581 (1981-12-01), Raghunathan
patent: 4482953 (1984-11-01), Burke
patent: 4538265 (1985-08-01), Day
patent: 4566103 (1986-01-01), Sato
patent: 4593391 (1986-06-01), Mizushima
patent: 4598402 (1986-07-01), Matsumoto
patent: 4639917 (1987-01-01), Furuta
patent: 4641305 (1987-02-01), Joyce
patent: 4661953 (1987-04-01), Uenkatesh

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