Computer processor with two addressable memories and two stream

Details Computer processor with two addressable memories and two stream Computer processor with two addressable memories and two stream

1997-11-07

1999-09-28

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712 1, 712 35, 712 36, 712208, 712220, 712221, 712223, 711100, 711116, 711220, G06F 1500

Patent

active

059580380

ABSTRACT:
A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation. The bits in the fields for specifying a stream register and addressing mode are positionally overlapped with the bits for specifying a particular general purpose register. This encoding allows a simple instruction decoding mechanism while enabling parallel memory accesses and address update in a compact instruction.

REFERENCES:
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patent: 5450555 (1995-09-01), Brown, III et al.
patent: 5455955 (1995-10-01), Kida et al.
patent: 5638524 (1997-06-01), Kiuchi et al.
patent: 5692207 (1997-11-01), Ho-Lung et al.
patent: 5805913 (1998-09-01), Guttag et al.

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