Computer processor with a replay system having a plurality of ch

Details Computer processor with a replay system having a plurality of ch Computer processor with a replay system having a plurality of ch

1998-07-31

2000-07-25

Coleman, Eric

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712244, G06F 938

Patent

active

060947179

ABSTRACT:
A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.

REFERENCES:
patent: 5519841 (1996-05-01), Sager
patent: 5784588 (1998-07-01), Leung
patent: 5835745 (1998-11-01), Sager
patent: 5870607 (1999-02-01), Netzer
patent: 5966544 (1999-10-01), Sager
patent: 5987594 (1999-11-01), Panwar
patent: 6006326 (1999-12-01), Panwar

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