Computer processor utilizing logarithmic conversion and method o

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364722, 3647485, 3642328, 3642584, 364DIG1, G06F 7556

Patent

active

056969864

ABSTRACT:
A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from the processing elements, an accumulator which sums converted values from the inverse-logarithm converter, and a control unit for configuring the accumulator to perform various summing operations. The computer processor also includes a switch for providing processor outputs as feedback. An instruction, selected from a set of instructions, is decoded by the control unit to configure the computer processor to perform operations on a data stream.

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patent: 5331582 (1994-07-01), Sudo et al.
patent: 5337266 (1994-08-01), Arnold
patent: 5359551 (1994-10-01), Pickett
patent: 5365465 (1994-11-01), Larson
patent: 5553012 (1996-09-01), Buss et al.
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities by Fang-shi Lai, and Ching-Farn Eric Wu, IEEE Transactions on Computers, vol. 40, No. 8, Aug. 1991, pp. 952-960.
A 3.84 GIPS Integrated Memory Array Processor with 64 Processing Elements and a 2-Mb SRAM by Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, and Masakazu Yamashima, IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1336-1343.

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