Patent
1995-03-31
1998-06-02
Treat, William M.
395391, G06F 900
Patent
active
057614750
ABSTRACT:
A processor is disclosed. The processor relates to a processor having a register file of registers and a dispatch unit capable of issuing up to (i) instructions of a program per cycle to an execution unit having (z) pipelines, wherein some of the instructions specify certain ones of the registers in the register file as source operands and designate certain ones of the registers in the register file as destination registers. The processor also includes a memory for storing the registers of the register file, the memory having (N) access ports configured to access up to (N) registers per cycle, where (N) is less than a maximum number of register values that may need to be accessed during a cycle.
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Wilhelm Neil
Yung Robert
Sun Microsystems Inc.
Treat William M.
Winder Patricia L.
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