Computer processor having a pipelined architecture which utilize

Details Computer processor having a pipelined architecture which utilize Computer processor having a pipelined architecture which utilize

1995-08-28

1997-08-12

Mai, Tan V.

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G06F 700

Patent

active

056572638

ABSTRACT:
A computer processor that performs operations in a logarithmic number system (LNS) domain includes an input log converter (20), a feedback log converter (303), a first data pipeline (304), a second data pipeline (306), a plurality of processing elements (26a-f) coupled to respective stages of the data pipelines, an inverse-log converter (28), and a programmable accumulator (232) which produces output signals. An instruction, selected from a set of instructions, is decoded by a control unit (235) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.

REFERENCES:
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Algorithm Design for a 30 bit Integrated Logarithmic Processor by David M. Lewis and Lawrence K. Yu, Department of Electrical Engineering, University of Toronto, Proceeding 9th Symposium on Computer Arithmetic, 1989, IEEE Comp. Soc. Pres, pp. 192-199.
An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System by David M. Lewis, Member, IEEE, IEEE Transactions on Computers, vol. 39, No. 11, Nov. 1990, pp. 1325-1336.
A 30-b Integrated Logarithmic Number System Processor by Lawrence K. Yu, Member, IEEE, and David M. Lewis, Member, IEEE, IEEE Journal of Solid-State Circuits, vol. 26, No. 10, Oct. 1991, pp. 1433-1440.
An Accurate LNS Arithmetic Unit Using Interleaved Memory Function Interpolator by Davd M. Lewis, Department of Electrical Engineering, University of Toronto, Proceeding 11th Symposium on Computer Arithmetic, 1993, IEEE Comp. Soc. Press, pp. 2-9.
Interleaved Memory Function Interpolators with Application on an Accurate LNS Arithmetic Unit by David M. Lewis, Member, IEEE, IEEE Transactions on Computers, vol. 43, No. 8, Aug. 1994, pp. 974-982.
Table-Lookup Algorithms for Elementary Functions and Their Error Analysis by Ping Tak Peter Tang, Matematics and Computers Schience Division, Argonne National Laboratory, 9700 S. Cass Ave., Argonne, IL 60439-4801, Proceeding 10th Symposium on Computer Arithmetic, Jun. 1991, pp. 232-236.
Applying Features of IEEE 754 to Sign/Logarithm Arithmetic by Mark G. Arnold, Member, IEEE, Thomas A. Bailey, Member, IEEE, John R. Cowles, and Mark D. Winkel, IEEE Transactions on Computers, vol. 41, No. 8, Aug. 1992, pp. 1040-1050.
D8 13 Improved Accuracy for Logarithmic Addition in DSP Applications by Mark G. Arnold, John Cowles, and Thomas Bailey, Computer Science Department, University of Wyoning, Laramie, WY, ICASSP 88: Int. Conf. on Acoustics, Speech and Signal Processing, vol. 3 pp. 1714-1717.
Redundant Logarithms Number Systems by M.G. Arnold, T.A. Bailey, J.R. Cowles, J.J. Cupal, University of Wyoming, Laramie, WY, Proceeding of 9th Symposium on Computer Arithmetic, pp. 144-151, IEEE Comp. Soc. Press.
Comments on "An Architecture for Addtion and Subtraction of Long Word Length Numbers in the Logarithmic Number System".sup.1 by M. Arnold, T. Bailey and J. Cowles, IEEE Transactions on Computers, vol. 41, No. 6, Jun. 1992, pp. 786-788.
Redundant Logarithmic Arithmetic, Mark G. Arnold, Member IEEE, Thomas A. Bailey, Member IEEE, John R. Cowles, and Jerry J. Cupal, Members IEEE,IEEE Transactions on Computers, vol. 39, No. 8, Aug. 1990, pp. 1077-1086.

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