Computer processing unit employing a separate millicode branch h

Details Computer processing unit employing a separate millicode branch h Computer processing unit employing a separate millicode branch h

1995-01-06

1997-05-27

Kim, Kenneth S.

395376, 395586, 395595, 395597, G06F 932

Patent

active

056341199

ABSTRACT:
A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table.
The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.

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