Electrical computers and digital processing systems: processing – Instruction fetching – Of multiple instructions simultaneously
Reexamination Certificate
2007-01-02
2008-11-18
Treat, William M (Department: 2181)
Electrical computers and digital processing systems: processing
Instruction fetching
Of multiple instructions simultaneously
C712S213000, C712S215000, C712S240000
Reexamination Certificate
active
07454597
ABSTRACT:
A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache. The scheduler creating the schedule using branch execution history from a branch history table to create the instructions when the schedule requested by the execution resource is not found in the schedule cache. The processor core executes the instructions according to the schedule being executed. The method includes requesting a schedule from a schedule cache. The method further includes fetching the schedule, when the schedule is found in the schedule cache; and creating the schedule, when the schedule is not found in the schedule cache. The method also includes renaming the registers in the schedule to avoid false dependencies in a processor core, mapping registers to renamed registers in the schedule, and stitching register values in and out of another schedule according to the list of register names and the rename map of registers.
REFERENCES:
patent: 5812810 (1998-09-01), Sager
patent: 6351802 (2002-02-01), Sheaffer
patent: 6704861 (2004-03-01), McKeen et al.
patent: RE38599 (2004-09-01), Tremblay
patent: 6892293 (2005-05-01), Sachs et al.
patent: 2002/0144088 (2002-10-01), Mohamed et al.
patent: 2003/0200396 (2003-10-01), Musumeci
patent: 2004/0148489 (2004-07-01), Damron
patent: 2004/0268098 (2004-12-01), Almog et al.
patent: 2005/0005084 (2005-01-01), Burger et al.
Black et al., “The Block-Based Trace Cache”, Proceedings of the 26th International Symposium on Computer Architecture, IEEE, May 2-4, 1999, pp. 196-207.
Talpes et al., “Execution Cache-Based Microarchitecture for Power-Efficient Superscalar Processors”; IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan. 2005, pp. 14-26.
Ravi Nair et al.; “Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups;” ACM 0-89791-901-7/97/0006; 1997; pp. 13-25.
Eric Rotenberg et al.; “Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching;” Apr. 11, 1996.
Kailas Krishnan K.
Nair Ravi
Sathaye Sumedh W.
Sauer Wolfram
Wellman John-David
Cantor & Colburn LLP
International Business Machines - Corporation
Treat William M
Wardas Mark
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