Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2008-07-01
2008-07-01
Ellis, Richard (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S043000, C712S229000
Reexamination Certificate
active
07395416
ABSTRACT:
A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after out-of-order execution when at least one of the plurality of processors is in an Instruction Level Parallelism (ILP) mode and at least one of the plurality of processors has a Thread Level Parallelism (TLP) core; detecting an imbalance in a dispatch of instructions of a first dependence chain compared to a dispatch of instructions of a second dependence chain with respect to dependence chain priority; determining a source of the imbalance; and activating the ILP mode when the source of the imbalance has been determined.
REFERENCES:
patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6311261 (2001-10-01), Chamdani et al.
patent: 7155600 (2006-12-01), Burky et al.
patent: 2005/0050303 (2005-03-01), Rosner et al.
patent: 2005/0071613 (2005-03-01), DeSylva et al.
Definition of “host system” from Wikipedia.org, accessed Mar. 16, 2008.
Definition of “computer” from Wikipedia.org, accessed Mar. 16, 2008.
Gurindar S. Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, vol. 39, Mar. 1990, pp. 349-359.
Leenstra et al., A 1.8-GHz Instruction Window Buffer for an Out-of Order Microprocessor Core, IEEE Journal of Solid-State Circuits, Vo. 36, No. 11, Nov. 2001, pp. 1628-1635.
Cantor & Colburn LLP
Ellis Richard
International Business Machines - Corporation
Mortinger Alison D.
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