Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2006-03-28
2006-03-28
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
Reexamination Certificate
active
07020763
ABSTRACT:
A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R×N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R×S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2. In accordance with yet another embodiment of the invention, a single VLIW processing instruction comprises R×N-number of P-bit sub-instructions appended together.
REFERENCES:
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4894770 (1990-01-01), Ward et al.
patent: 4980819 (1990-12-01), Cushing et al.
patent: 5184320 (1993-02-01), Dye
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5301340 (1994-04-01), Cook
patent: 5317718 (1994-05-01), Jouppi
patent: 5386547 (1995-01-01), Jouppi
patent: 5530817 (1996-06-01), Masubuchi
patent: 5564035 (1996-10-01), Lai
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5588130 (1996-12-01), Fujishima et al.
patent: 5623627 (1997-04-01), Witt
patent: 5649154 (1997-07-01), Kumar et al.
patent: 5650955 (1997-07-01), Puar et al.
patent: 5687338 (1997-11-01), Boggs et al.
patent: 5703806 (1997-12-01), Puar et al.
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5900011 (1999-05-01), Saulsbury et al.
patent: 5953738 (1999-09-01), Rao
patent: 6000007 (1999-12-01), Leung et al.
patent: 6128700 (2000-10-01), Hsu et al.
patent: 6128702 (2000-10-01), Saulsbury et al.
patent: 6202143 (2001-03-01), Rim
patent: 6256256 (2001-07-01), Rao
patent: 6275900 (2001-08-01), Liberty
patent: 6317820 (2001-11-01), Shiell et al.
patent: 6321318 (2001-11-01), Baltz et al.
patent: 6401190 (2002-06-01), Nishioka et al.
patent: 6418527 (2002-07-01), Rozenshein et al.
patent: 6629232 (2003-09-01), Arora et al.
patent: 2001/0042187 (2001-11-01), Tremblay
patent: WO 00/33178 (2000-06-01), None
Aimoto, Yoshiharu et al.; “A.768GIPS 3.84GB/s 1 W Parallel Image-Processing RAM Integrating a 16 Mb DRAM and 128 Processors”; ISSCC96/Session 23 / DRAM / Paper SP23.3; 1996 IEEE International Solid-State Circuits Conference; pp. 372-373 and 476.
Bursky, Dave; “Combo RISC CPU and DRAM Solves Data Bandwidth Issues”; Electronic Design; Mar. 4, 1996; pp. 67-71.
Saulsbury, Ashley, et al., “Missing the Memory Wall: The Case for Processor/Memory Integration”; ACM; 1996; pp. 90-101.
Shimizu, Toro, et al.; “A Multimedia 32b RISC Microprocessor with 16 Mb DRAM”; ISSCC96/Session 13 / Microprocessors/Paper FP 13.4; 1996 IEEE International Solid State Circuts Conference; pp. 216-217 and 448.
Mitsubishi Electric Corp; Product Specification for Single-Chip 32-Bit CMOS Microcomputer, May 1998.
Numomura Y et al: “M32R/D-IntegratingDRAM and Microprocessor” IEEE Micro, IEEE Inc. New York, US, vol. 17 No. 6, Nov. 1, 1997, pp. 40-48, XP000726003; ISSN:0272-1732.
Kozyrakis C E et al: “Scalable Processors in the Billion-Transistor Era: IRAM” Computer IEEE Computer Society, Long Beach., CA, US, US vol. 20, No. 0 Sep. 1, 1997, pp. 75-78, XP000730003; ISSN:0018-9162.
Herrmann Klaus, Hilgenstock Joerg, Pirsch Peter: “Architecture of a Multiprocessor System With Embedded DRAM For Large Area Integration” Oct. 8, 1997, IEEE International Conference on Innovative Systems in Silicon, Piscataway, NJ, USA; XP002179990.
Parkin Michael
Rice Daniel S.
Saulsbury Ashley
Sun Microsystems Inc.
Treat William M.
LandOfFree
Computer processing architecture having a scalable number of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer processing architecture having a scalable number of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer processing architecture having a scalable number of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3541333