Computer peripheral control apparatus

Boots – shoes – and leggings

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G06F 1516, G06F 1506

Patent

active

044868260

ABSTRACT:
A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.
Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.
The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

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"Pluribus--An Operational Fault-Tolerant Multiproccesor"--Katsuki Proceedings of the I.E.E.E. vol. 66, No. 10--Oct. 1978, pp. 1146-1159.
"Architectures for Fault Tolerant Spacecraft Computers"--Rennels Proceedings of the I.E.E.E. vol. 66, No. 10, Oct. 1978.
"N-Fail Safe Logical Systems"--Takaoka--I.E.E.E. Transactions on Computers vol. C-20 No. 5, May 1971, pp. 536-542.
"Fault Tolerant Microcomputer Systems for Aircraft" Conference: Conference on Computer Systems and Technology, Brighton, Sussex, England, Mar. 29-31 1977--Author Depledge.
Anderson & Lee, Fault Tolerance, Principles and Practice Prentice-Hall International, New Jersey, 1981.

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