Electrical computers and digital processing systems: multicomput – Bused computer networking
Reexamination Certificate
1998-12-24
2001-10-09
Luu, Le Hien (Department: 2152)
Electrical computers and digital processing systems: multicomput
Bused computer networking
C709S245000, C709S250000, C370S489000
Reexamination Certificate
active
06301623
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to a computer network with a plurality of communication channels feeding into a single management channel where a device on each of the communication channels all have an identical address. The present invention relates in particular to a network concentrator and the management of the devices on a plurality of cards in the concentrator.
BACKGROUND OF THE INVENTION
A network concentrator contains a plurality of modules for connecting together a plurality of stations. These modules can be roughly divided into management modules and communication or media modules. The communication modules connect to links which in turn connect to individual stations, or to other concentrators. The management modules control the operation of the communication modules, and the interaction between the communication modules. Management modules include modules which supply power to the communication modules, and modules which recognize and configure the communication modules for proper operation and interoperation.
In order for a management processor to recognize and configure the communication modules, the management processor must be able to read from, and write to, the individual devices on the communication and other modules. Because of the number of devices on a module, and the amount of communication involving these devices, it has been preferable to connect all the devices on a module to a common bidirectional serial channel. Each of the devices in the module has a unique address and can communicate with a management processor by sending or receiving a packet of information with the proper address.
As the size of computer networks grow, the number of stations increase, and correspondingly the number of communication modules in a concentrator increases. Also management modules, and particular the processor means of the management module are becoming more advanced, reducing in size, and in particular have a communication port with a single lead that is bidirectional.
A difficulty arises in that a single bidirectional lead of a microprocessor must be connected to each channel of a plurality of communication modules, where because of the limited number of addresses on the channels, and the large number of modules, several devices will have identical addresses. Digital multiplexing and digital demultiplexing have been previously used when the management processor had separate transmit and received ports for leads. However, digital multiplexers and demultiplexers are not bidirectional and therefore cannot be used with a bidirectional port or pin of a management processor.
SUMMARY AND OBJECTS OF THE INVENTION
It is a primary object of the present invention to allow communication between a bidirectional port of a management processor to a plurality of devices connected to different bidirectional serial channels, where devices on different channels may have identical addresses.
The present invention accomplishes this object by connecting each bidirectional serial channel of a plurality of devices to an output of an analog multiplexer. Although analog multiplexer posts are referred to as “input”and “output”, they are, in fact, bidirectional. The bidirectional port of the management processor is connected to the input of the analog multiplexer. A selection means selects one of the serial channels for communication with the management processor, and generates a selection signal which is sent to the multiplexer. The multiplexer reads the selection signal, and connects the input of the multiplexer to the selected output of the multiplexer, where the output of the multiplexer is connected to the desired serial channel. Since an analog multiplexer is similar to a selection switch and is bidirectional, the management processor can communicate with the selected serial channel through the bidirectional port of the management processor.
The selection means can be part of the management processor, in which case the selection signal is transmitted from the management processor to the multiplexer. In an alternative, a device register can be connected to the bidirectional port of the management processor and receive data packets from the management processor. The data packets indicate one of the serial channels. The device register reads the packet and generates the selection signal based on the packet. This second embodiment is useful if the management processor is unable to send the selection signal directly to the multiplexer, due to such factors as the distance between the microprocessor and the multiplexer being too large to provide separate leads for the selection signal, or due to the processor not having enough outputs for a selection signal. The selection signal for a multiplexer is often a parallel signal requiring a plurality of individual signals, each with their own lead.
If the device register is used, there must be an available unique address for the device register so that the management processor can communicate with the device register over the bidirectional serial channel.
The present invention allows a management module to use a management processor with a bidirectional channel to communicate with a plurality of communication modules, where each communication module has its own bidirectional serial channel and devices which have channel addresses that are identical to the devices of other modules. The second embodiment is in particular advantageous, when the dividing of the lead from the bidirectional port of the management module into the separate channels of the communication modules occurs at a great distance from the management module.
In the preferred embodiment of the present invention, the bidirectional serial channel is an Inter-Integrated Circuit (
1
2
C or 12C —developed by Philips Semiconductors) bus with a clock and a bidirectional serial data line intended to allow communication between integrated circuits (ICs). Each circuit on the bus has an address which consists of a part code and three user-configurable address bits. This would normally allow a maximum of eight of each type of IC to be connected to a single bus. The addressing capability can be expanded by using a simple bidirectional analog multiplexer to select among several destination busses.
The present invention allows expansion of I2C addressing, virtually without limit, by using a digitally controlled switching unit (analog multiplexer) to connect separate I2C busses to a common controller device. This allows addressing of multiple networks whose I2C devices may have overlapping device addresses. Additionally, in a second embodiment, the invention is expanded to allow this switching function to occur over the I2C bus itself, by use of an I2C register device to control the multiplexer selection inputs.
The I2C bus can be used in a network concentration in two places. One I2C bus is used by the management processor Enterprise Management Engine (EME) to read serial EEPROMs on each module installed in the concentrator. Another bus is used by the switch fabric to communicate with the Gigabit EtherNet I/O (GENIO) blades.
In a first embodiment, each slot or module has its own data line and all slots share two common clock lines (only one of which is active at any time). Each slot can contain up to 8 devices of the same type connected to each of the two clock lines and the common slot data line. This means that a concentrator with 16 slots times 8 devices of the same type per slot has 128 same type devices. Previous designs (with separate transmit and receive multiplexers) weren't useable, with a Motorola MPC860 processor that has only one bidirectional data pin. The present invention uses an analog multiplexer (basically a multiposition selector switch) to route the bidirectional data line to one of 16 possible slots.
A second embodiment involves four identical type I2C devices whose user address bits are hardwired to the same address. These four devices can not coexist on the same I2C bus. The present invention uses an I2C device register (the Philips PCF8574
Blacker Kurt
Kimmitt Myles
Simpson Peter
3Com Corporation
Luu Le Hien
McGlew & Tuttle P.C.
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