Computer modified to perform inverse discrete cosine transform o

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G06F 1714

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058019758

ABSTRACT:
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

REFERENCES:
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Kohn, L, et al., "The Visual Instruction Set (VIS) in UltraSPARC," SPARC hnology Business--Sun Microsystems, Inc., 1996 IEEE, pp. 462-489.
Gwennap, Linley, "UltraSparc Adds Multimedia Instructions --Other New Instructions Handle Unaligned and Little-Endian Data," Microprocessor Report, Dec. 5, 1994, pp. 16-18.
Lee, Ruby B., "Realtime MPEG Video via Software Decompression on a PA-RISC Processor," Hewlett-Packard Company, 1995 IEEE, pp. 186-192.
Mattison, Phillip E., "Practical Digital Video With Programming Examples in C," Wiley Professional Computing, pp. 158-178, 1994.
Zhou, Chang-Guo, et al., "MPEG Video Decoding With the UltraSPARC Visual Instruction Set," Sun Microsystems, Inc., 1995 IEEE, pp. 470-474.

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