Computer memory refresh circuit

Details Computer memory refresh circuit Computer memory refresh circuit

1984-11-26

1989-01-31

Heckler, Thomas M.

Boots, shoes, and leggings

340750, 340799, 365222, G09G 100, G09G 104

Patent

active

048021180

ABSTRACT:
This invention is so arranged that, in a dynamic random access memory including a display memory area storing therein the display data and a system memory area employed for arithmetic operation in a central processing unit, memory refresh is accomplished by a display address signal applied to the dynamic random access memory when information stored in the dynamic random access memory is utilized for display, and a refresh address signal from a refresh counter for generating such a refresh address signal is applied to the random access memory as a burst signal for a predetermined period at predetermined intervals during a display frame time, thus refreshing memory, when information stored in the dynamic random access memory is not utilized for display.

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patent: 4661812 (1987-04-01), Ikeda
patent: 4665495 (1987-05-01), Thaden
Zaks, Rodney; "Microprocessors from Chips to Systems," pp. 55-56, SYBEX, 1980.

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