Computer memory read delay

Details Computer memory read delay Computer memory read delay

1974-04-15

1976-10-05

Botz, Eugene G.

Communications: electrical

Digital comparator systems

G06F 920

Patent

active

039848124

ABSTRACT:
Disclosed is a digital computer memory system which coordinates between plural memories such that information recall from memories having different inherent access times results in a flow of only relevant data to the processor; this is accomplished in, for instance, a dual memory system, by synchronizing the operation of the memories such that the normal clock pulse of the computer strobes the output register of the faster (i.e., "normal") memory but a delayed clock pulse strobes the output register of the slower memory. Thus, because of the delayed strobe, the latter, as well as the former, has time to complete an access requested by the processor, and, consequently, transfer to the processor of incorrect or meaningless information is avoided. This system is incorporated in the computer in the form of additional registers, memory elements, gates and arithmetic circuits, which recognize addresses as falling within either memory, energize the appropriate memory and excite it for read out with either a normal or delayed strobe as determined by its identification as the fast or slow memory, respectively.

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patent: 3763474 (1973-10-01), Freeman et al.
patent: 3810119 (1974-05-01), Zieve et al.

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