Computer memory data merging technique for computers with write-

Details Computer memory data merging technique for computers with write- Computer memory data merging technique for computers with write-

1991-09-18

1996-06-25

Kim, Matthew M.

Boots, shoes, and leggings

395448, 395470, 364DIG1, 3642281, 36424344, G06F 1208

Patent

active

055308350

ABSTRACT:
A memory controller intercepts data bytes destined for a memory and selectively combines them with data bytes previously read from the memory. The controller also blocks data bytes destined for the memory corresponding to data bytes previously written to the memory. The memory controller includes an input device and an output device. An output line of the input device is connected to both the memory and an input line of the output device. Also, the memory is connected to the input line of the output device.

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"82385 High Performance 32-Bit Cache Controller"; pp. 1-11; Oct. 1987; printed in U.S.A.

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