Computer memory array control for accessing different memory ban

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39518204, 364DIG1, 3642689, 364DIG2, 36494461, 3649456, 3649521, 3649665, G06F 1110, G06F 1316

Patent

active

055265073

ABSTRACT:
A computer memory controller for interfacing to a host computer comprises a buffer memory for interfacing to a plurality of memory units and for holding data read thereto and therefrom. A central controller is operative to control the transfer of data to and from the host computer and the memory units. The buffer memory is controlled to form a plurality of buffer segments for addressably storing data read from or written to the memory units. The central controller is operative to allocate a buffer segment for a read or write request from the host computer, of a size sufficient for the data. The central controller is also operative in response to data requests from the host computer to control the memory units to seek a plurality of requested data stored in different memory units simultaneously.

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patent: 5187778 (1993-02-01), Yamamoto et al.
patent: 5301297 (1994-04-01), Menon et al.
patent: 5303244 (1994-04-01), Watson
"Raid Aid: A Taxonomic Extension of the Berkeley Disk Array Schema"; Storage Computer Corporation; 1991; pp. 1-4.

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