Boots – shoes – and leggings
Patent
1985-07-02
1988-08-02
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 1300
Patent
active
047617306
ABSTRACT:
A memory subsystem couples to a bus in common with and proceses memory requests received therefrom. The subsystem includes a single addressable memory module unit or stack having a number of word blocks of dynamic random access memory (DRAM) chips mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. Chip select circuits preselect a pair of blocks of RAM chips from the stack. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the sequential read out of a pair of words from the preselected blocks of the single word wide module into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out in sequence providing a double fetch capability without any loss in system performance.
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patent: 4174537 (1979-11-01), Chu et al.
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patent: 4323965 (1982-04-01), Johnson et al.
patent: 4361869 (1982-11-01), Johnson et al.
patent: 4628489 (1986-12-01), Ong et al.
Fisher Edwin P.
Ng Alvan W.
Chun Debra A.
Driscoll Faith F.
Honeywell Bull Inc.
Shaw Gareth D.
Solakian John S.
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