Computer look-ahead instruction issue control

Details Computer look-ahead instruction issue control Computer look-ahead instruction issue control

1989-01-17

1992-06-30

Eng, David Y.

Boots, shoes, and leggings

3642631, 3642816, 364948, G06F 938

Patent

active

051270935

ABSTRACT:
A system for scheduling instruction issuance in a vector register computer achieves increased efficiency of operation by performing pre-issuance checks to determine if resources requested by the instruction will be available when the instruction issues. A decoding apparatus first determines particular resources requested by the instruction, which includes apparatus for decoding vector register requests, functional unit requests, and address and scalar register path requests. Following decoding, a conflict resolution apparatus checks resource reservation flags to determine if the requested resources will be available when the instruction issues. If any requested resources will be busy, the system issues a primary conflict signal. At the scheduled instruction issuance time, the system again checks the resource reservation flags in response to the primary conflict signal. If the requested resources are still busy, the system generates a secondary conflict signal for as long as the requested resources remain busy. Finally, when the instruction issues, the system sets the resource reservation flags to reserve the requested resources for the instruction.

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"The Cray-2 Engineering Maintenance Manual, CMM 0200000", Dec. 1987, pp. 4--1 through 4--3.
IBM Journal of Research and Development, vol. 11, No. 1, Jan. 1967; D. W. Anderson et al.: "The IBM System/360 Model 91: Machine Philosophy and Instruction-handling".
IBM Technical Disclosure Bulletin, vol. 27, No. 5, Oct. 1985, Capozzi, et al.: "Non-sequential High-performance Processing".
IEEE Transactions on Computers, C-33 No. 11, Nov. 1984, IEEE, Weiss et al; "Instruction Issue Logic in Pipelined Supercomputers".

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