Computer interface circuit

Details Computer interface circuit Computer interface circuit

1992-12-23

1994-03-01

Fleming, Michael R.

Boots, shoes, and leggings

395325, 3642383, 3642385, 3642412, 3642413, 364244, 3642443, 364DIG1, G06F 1314

Patent

active

052916090

ABSTRACT:
An interface circuit for providing asynchronous interrupt service for multiple peripheral devices in accordance with instructions from a host computer includes two dual universal asynchronous receivers-transmitters ("UARTs"), a dual port random-access memory ("RAM") and a microprocessor (".mu.P"). The dual UARTs selectively read data separately from selected peripheral devices and selectively write that data to the dual port RAM for access by the host computer, and read data from the dual port RAM as stored therein by the host computer and write that data to a selected peripheral device, in accordance with addresses from the .mu.P. Following initiation of an interrupt sequence, the dual port RAM allows the host computer to selectively and asynchronously read data (e.g. from a peripheral device via a dual UART) therefrom and write necessary data or instructions (e.g. for the .mu.P or a peripheral device via a dual UART) thereto for the .mu.P to asynchronously provide interrupt service to the peripheral devices. This interface circuit configuration minimizes idle time for the host computer during interrupt servicing by the .mu.P.

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