Boots – shoes – and leggings
Patent
1982-07-29
1985-04-23
Thomas, James D.
Boots, shoes, and leggings
G06F 938, G06F 1300
Patent
active
045133719
ABSTRACT:
This apparatus is used for minimizing the performance degradation due to address translation in computer systems employing random access memory and paging. It translates initial addresses into real addresses utilizing addressable memory and substitute paging. It decreases access time by not translating virtual address bits that are also real address bits and by commencing memory access using the available real address bits as they are available.
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patent: 4340932 (1982-07-01), Bakula et al.
patent: 4388685 (1983-06-01), Kotok
patent: 4403283 (1983-09-01), Myntti et al.
patent: 4410941 (1983-10-01), Barrow et al.
patent: 4447877 (1984-05-01), Grondalski
Cavender J. T.
Dugas Edward
NCR Corporation
Thomas James D.
Williams Archie E.
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