1994-09-16
1997-04-08
Auve, Glenn A.
395452, 395464, G06F 938
Patent
active
056196636
ABSTRACT:
An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction fetch unit, to which is added a second instruction prefetch buffer in the system, preferably in the bus interface unit which serves as the memory interface unit. This added prefetch buffer has storage for only a small number of bytes or words, and operates to supply prefetched instructions to the queue in the instruction fetch unit. However, it operates under the following constraint: it only prefetches within the boundaries of each small block of code memory and stalls when a block boundary is reached until a new address appears. This approach combines some cache and prefetch principles for a limited cost design.
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Goodhue Gregory K.
Mizrahi-Shalom Ori K.
Ostler Farrell L.
Auve Glenn A.
Philips Electronics North America Corp.
Stephens Debra K.
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