Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Mechanical measurement system
Reexamination Certificate
2002-08-21
2004-05-25
Bui, Bryan (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Mechanical measurement system
C702S084000, C702S181000, C700S110000, C700S121000
Reexamination Certificate
active
06741940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer-implemented method of defect analysis for analyzing failure causes such as electrical properties on a semiconductor device on which presence/absence of defects can be checked at some point in a manufacturing process.
2. Description of the Background Art
As a background-art defect analysis method for analyzing failure causes such as electrical properties on a semiconductor device on which presence/absence of defects can be checked at some point in a manufacturing process, an analysis method is disclosed in Japanese Patent Application Laid Open Gazette No. 11-264797.
Disclosed in the above gazette is a defect analysis method paying its attention to new defects caused in a predetermined process step among a plurality of manufacturing process steps. The background-art defect analysis method will be discussed below in detail.
For specific discussion, devices are manufactured through six process steps A, B, C, D, E and F and the devices are subjected to a defect inspection by an inspection apparatus after each of the process steps A to F.
It is assumed, for example, that a process for manufacturing a DRAM consists of six process steps, i.e., the process step A of forming patterns of underlying oxide films, the process step B of forming transistors (for memory cell array, for controlling the memory cell array and the like), the process step C of forming capacitors (for memory cell), the process step D of forming (interlayer) insulating films, the process step E of forming metal wires (in the direction of row) and the process step F of forming metal wires (in the direction of column).
In the following discussion, the process step D is regarded as the predetermined process step to make an analysis.
First, new defects caused in the process step D are extracted. In this case, as shown in
FIG. 17
, there are a lot of defects
5
, such as pattern defects, foreign matters, contaminant deposition and damages, which are detected on a wafer map
4
after the process step D. Among the defects
5
on the wafer map
4
, defects caused only in the process step D are judged to be new defects
9
, which are present on new regions other than coordinates of new defects
6
to
8
on wafer maps
1
to
3
, which are already detected in the process steps A to C precedent to the process step D, and coordinates of defect neighborhood regions including error ranges
15
.
Specifically, as shown in the graph of
FIG. 18
, the number of defects which is obtained by subtracting the number of new defects
6
to
8
detected in the process steps A to C and the number of defects on the same coordinates as the error ranges
15
from the total number of defects
5
on the wafer map
4
of the process step D corresponds to the number of new defects
9
.
Next, after the process steps A to F are finished, a judgment result of pass/fail is obtained on respective integrated circuits formed on all the chips on a wafer with an electrical tester for judging pass/fail on an electrical operation. Further, the electrical tester generally performs a pass/fail test on the basis of a comprehensive result obtained through a plurality of partial electrical tests each for judging pass/fail on a specific electrical property.
Then, as shown in
FIG. 19
, a plurality of extracted chips on which presence/absence of the new defects
9
caused only in the process step D is judged and a plurality of chips on which pass/fail is judged as above are collated on a wafer map
20
. As shown in
FIG. 19
, there are 52 new defects caused in the process step D, which are distributed in 45 chips. There are 78 faulty chips detected by the electrical tester and 57 good chips, totally 135 chips.
These 135 chips are classified by chips into four sorts, i.e., {circle around (1)} 48 good chips without defect, {circle around (2)} 42 faulty chips without defect, {circle around (3)} 9 good chips with defect and {circle around (4)} 36 faulty chips with defect, as shown in FIG.
20
.
In this defect analysis method, even a chip with more than one defect is classified into the same category of “with defect” as a chip with only one defect. Though there is another method in which a chip with more than one defect is weighted accordingly, in this defect analysis method, calculation proceeds without weighting. After this point, the number of defects is not involved in this analysis procedure and counting is made simply on the number of chips with defect. Therefore, since a chip with collective defects is regarded as a chip in the class {circle around (3)} or {circle around (4)}, classification considering little effect of collective defects can be performed.
Herein discussion will be made on the meaning of classification of the chips into four sorts. The classes {circle around (3)} and {circle around (4)}, which include the chips with defect, are affected by the process step D. In contrast to this, the classes {circle around (1)} and {circle around (2)} are unaffected by the process step D. Accordingly, the classes {circle around (1)} and {circle around (2)} have better yield than the classes {circle around (3)} and {circle around (4)}. The classes {circle around (1)} and {circle around (2)}, however, are affected by any one of the five process steps A, B, C, E or F. Therefore, if the classes {circle around (3)} and {circle around (4)} are unaffected by the process step D, it can be supposed that the classes {circle around (3)} and {circle around (3)} should have the same yield as the classes {circle around (1)} and {circle around (2)}.
The rate of failure RB1 (=1—the rate of good=1—yield) of the classes {circle around (1)} and {circle around (2)} is expressed as the following equation (1), wherein it is assumed that {circle around (1)} the number of good chips without defect is N1, {circle around (2)} the number of faulty chips without defect is N2, {circle around (3)} the number of good chips with defect is N3 and {circle around (4)} the number of faulty chips with defect is N4.
RB1
=
N2
(
N1
+
N2
)
=
42
(
48
+
42
)
(
1
)
Applying Eq. 1 to the classes {circle around (3)} and {circle around (4)}, the number NE of faulty chips which are affected by any one of the five process steps A, B, C, E or F other than the process step D is obtained as the following equation (2):
NE
=(
N
3
+N
4)×
RB
1=(9+36)×
RB
1=21 (2)
Since the actual number of faulty chips in the classes {circle around (3)} and {circle around (4)} is the number of chips in the class {circle around (4)}, the number N0 of new faulty chips which are estimated to be failed only by the new defects caused in the process step D is obtained as the following equation (3):
N
0
=N
4
−NE=
36−21=15 (3)
Next, the fatality rate RF of the new defects in the process step D is calculated. From the relation between the rate of failure RB1 in the classes {circle around (1)} and {circle around (2)} and the rate of failure RB3 in the classes {circle around (3)} and {circle around (4)}, i.e., RB3=N4/(N3+N4)=36/(9+36), the effect of the process step D is considered. Suppose that distribution of defects caused in the process step D is uniform in the areas {circle around (3)} and {circle around (4)}, the rate of good RG in the process step D is obtained as the following equation (4), according to the law of probability product, on the basis of the rate of good rg1 (=N1/(N1+N2)) in the classes {circle around (1)} and {circle around (2)} and the rate of good rg3 (=N3/(N3+N4)) in the classes {circle around (3)} and {circle around (4)}.
RG
=
rg3
rg1
=
0.375
(
4
)
Accordingly, the fatality rate RF of the new defects in the process step D is determined by the following equation (5):
RF=
1
−RG=
0.625 (5)
This means that 62.5% out of the chips with new defect which are detected by the inspection apparatus are fatal. In this case, the inspection appa
Hattori Nobuyoshi
Mugibayashi Toshiaki
Bui Bryan
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
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