Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-06-19
2001-03-06
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06199083
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer implemented interpolation methods.
BACKGROUND OF THE INVENTION
Interpolation is a well known procedure for determining a value corresponding to a point based on known values corresponding to surrounding points. Methods and I apparatus for performing interpolation on computer systems can be critical to the user acceptance of certain computer applications.
For instance, many of the most advanced computer applications use three dimensional graphics that require texture mapping, i.e., mapping an image, or a texture map, onto a surface, such as an area in a pixel map to be displayed. A prior approach to texture mapping uses nearest neighbor sampling, wherein a color value for a display pixel is chosen to be the color value for the nearest texel, i.e., the nearest point in the texture map. However, this prior approach can result in undesirable jerky animation, because a small change in the texture map can cause dramatic changes in the nearest pixels.
Smoother animation can be achieved by using an approach involving bilinear interpolation. With bilinear interpolation, a color value for a display pixel is chosen by calculating a weighted average of the four nearest texels. However, using known methods and apparatus for bilinear interpolation on a computer system requires processor intensive iterations that degrade frame rates. Many application developers are unwilling to sacrifice high frame rates for smoother animation. Therefore, a novel approach to bilinear interpolation on a computer system has been developed.
SUMMARY OF THE INVENTION
A method for interpolating a value corresponding to a point represented by at least two binary coordinates, each binary coordinate having a fractional portion, is disclosed. The method includes a computer implemented step of multiplying together the fractional portions of at least two of the binary coordinates to generate a first sigma value. The method also includes the computer implemented steps of inverting each bit of the first sigma value to generate an inverted first sigma value, and adding the fractional portion of at least one of the binary coordinates to the inverted first sigma value to generate a second sigma value.
REFERENCES:
patent: 5345541 (1994-09-01), Kelley et al.
patent: 5402533 (1995-03-01), Kelley et al.
patent: 5922043 (1999-07-01), Mais
patent: 5935198 (1999-08-01), Blomgren
Blakely, Sokloff, Taylor & Zafman LLP
Intel Corporation
Mai Tan V.
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