Computer implemented method for generating an integrated circuit

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364488, 364489, 364491, G06F 1750

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active

055860460

ABSTRACT:
A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.

REFERENCES:
patent: 5396435 (1995-03-01), Ginetti
"A Schematic Driven Synthesis Tool for Analog Circuits"; European ASIC; B. Goffert et Al., 1992; pp. 131-134.
"STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits"; J. Harvey et al; IEEE Transactions on Computer Aided Design; vol. 11, Nov. 1992; pp. 1402-1417.
"Optimiztion-Based Placement Algorithm for BiCMOS Leaf Cell"; Hongxia Xia et al.; IEEE Journal of Solid State Circuits, vol. 29, No. 10, Oct. 1994; pp. 1227-1236.

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