Computer having a single bus supporting multiple bus architectur

Details Computer having a single bus supporting multiple bus architectur Computer having a single bus supporting multiple bus architectur

1995-05-26

1997-05-13

An, Meng-AI T.

Boots, shoes, and leggings

39520013, 395281, 395282, 395297, 395306, 395307, 395865, 395869, 364238, 3642382, 3642383, 3642389, 364DIG1, G06F 1300

Patent

active

056301634

ABSTRACT:
A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.

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